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Additional info for IEEE Std 1800-2009: IEEE Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language

Sample text

532 Table 20-7—Types of queues of $q_type values ....................................................................................... 536 Table 20-8—Argument values for $q_exam system task............................................................................ 537 Table 20-9—Status code values ................................................................................................................. 537 Table 20-10—PLA modeling system tasks ................................................................................................

452 Syntax 18-8—Static constraint syntax (excerpt from Annex A) ................................................................. 453 Syntax 18-9—In-line constraint syntax (excerpt from Annex A) ............................................................... 459 Syntax 18-10—Scope randomize function syntax (not in Annex A) .......................................................... 465 Syntax 18-11—Randcase syntax (excerpt from Annex A)..........................................................................

Annex B (normative) lists the SystemVerilog keywords. Annex C (informative) lists constructs that have been deprecated from SystemVerilog. The annex also discusses the possible deprecation of the defparam statement and the procedural assign/deassign statements. Annex D (informative) describes system tasks and system functions that are frequently used, but that are not required in this standard. Annex E (informative) describes compiler directives that are frequently used, but that are not required in this standard.

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